Nanomaterials in Semiconductor Packaging: Challenges and Opportunities
David Xu, Intel
Packaging of semiconductor devices essentially transforms semiconductor devices into functional electronic products. Packaging technology not only establishes the shape, size, and weight of chips, but also determines the chip reliability. While packaging has always been an important technology enabler, in recent years with increasing need for heterogeneous integration, the scope and demand on packaging materials has been expanded to include the newer and increasingly diverse high-density packaging architectures for system in package (SiP). These include 2D and 3D architectures and cover wafer level packaging, integrated passive device (IPD), through silicon via (TSV), 3D packaging, etc. Packaging materials are becoming critical for enabling the heterogeneously integrated next-generation chips and their intra-package and inter-package interconnects. This calls for innovations in packaging materials to deliver the optimized electrical, thermal, and mechanical properties. Certainly, nanomaterials and nanotechnology have been used in packaging technologies for the past few decades, and nanoparticles will continue to play an important role in providing solutions for future packaging challenges and bottlenecks. In this talk, we plan to provide insights into nanomaterials which have demonstrated potentials for electronic packaging applications as well as highlight the emerging nanotechnology trends. We end with a call to all academic and industrial partners to collaborate and deliver on the promise.
David Xu received his Ph.D. in Chemistry from Virginia Tech, and M.S. in Polymer Science and Engineering from Lehigh University. David joined Intel in 2004 in Materials Technology Development in Chandler as a Sr. Packaging Engineer developing assembly materials for communication and wireless packages. He went on to lead materials pathfinding and development for various assembly materials for IC packaging over the last 16 years. His area of expertise is in various polymer materials/encapsulant, adhesives, films for IC packaging assembly. He has developed a number of novel materials technologies that have enabled critical Intel assembly package assembly and process. In recent years, he assumed the role of assembly materials pathfinding lead and is responsible for setting strategic direction and developing materials technology roadmap to enable Intel’s next generation heterogonous packaging.